1. Field of the Invention
The present invention relates to a synchronous type semiconductor memory device operating in synchronization with an external clock signal and more particularly to a synchronous type semiconductor memory device outputting both of data and a read clock signal which determines timing for sampling the data. More specifically, the present invention relates to a circuit for adjusting timing for outputting a read clock signal which in turn is output at the time of data reading.
2. Description of the Background Art
In order to transfer data at high speed in accordance with the high speed operation of a processor, a synchronous type semiconductor memory device which inputs/outputs data in synchronization with an external clock signal such as a system clock has been used extensively as a main memory. One of such synchronous type semiconductor memory devices is a sync link DRAM (SLDRAM: Sync Link Dynamic Random Access Memory).
FIG. 10 shows an example of the structure of a memory system in which the sync link DRAMs are used. In FIG. 10, the memory system includes eight sync link DRAMs S#0-S#7 and a controller 900 for controlling access to these sync link DRAMs S#0-S#7.
Sync link DRAMs S#0-S#7 are commonly coupled to a control clock line 902 transmitting a control clock signal CCLK supplied from controller 900, a command/address bus 904 transmitting a command designating an operation mode and an address indicating a memory location to be accessed, a data clock line 906 transmitting a data clock signal DCLK which provides timing for writing/reading of data, and a data bus 908 transmitting write/read data. Control clock line 902 and command/address bus 904 are unidirectional buses which transmit control clock signal CCLK and the command/address which in turn are output from controller 900 in one direction. On the other hand, data clock line 906 and data bus 908 are bi-directional buses which transmit data clock signal DCLK and data bi-directionally between controller 900 and sync link DRAMs S#0-S#7.
Sync link DRAMs S#0-S#7 are identified by an identifier called a slave ID. In a sync link DRAM designated by the slave ID transmitted on command/address bus 904 from controller 900, an operation designated by a command is performed. A data reading operation in the memory system shown in FIG. 10 will now be described with reference to a timing chart shown in FIG. 11.
At the time of data reading, in synchronization with clock signal CCLK supplied to control clock line 902, controller 900 provides a command in a packet form instructing data reading to command/address bus 904. The read request command also includes a slave ID specifying a sync link DRAM, and the sync link DRAM designated by the slave ID takes in a command applied on command/address bus 904 at both of the rising and falling edges of control clock signal CCLK. In the designated sync link DRAM, data is read and, after prescribed latency, read clock signal DCLK and data D0 are output to data bus 908.
The data appeared on data bus 908 changes in synchronization with the both rising and falling edges of read clock signal DCLK, and eight data D0-D7 are successively output over clock cycles #7-#10. The time period required from application of a read request command to actual reading of data is called "read latency", and the number of data successively read by one command is called "burst length". Read clock signal DCLK (used likewise during writing as well) on clock signal line 906 is at a high impedance state in a standby cycle. Before data reading, the designated sync link DRAM once lowers read clock signal DCLK to the low level and then activates read clock signal DCLK in a cycle preceding by one cycle clock cycle in which data is actually read out.
Read clock signal DCLK is generated based on control clock signal CCLK, and controller 900 samples data appeared on data bus 908 in accordance with read clock signal DCLK. Since the distance from controller 900 is different for each sync link DRAM, the timing for generating read clock signal DCLK is shifted in accordance with the distance from controller 900, in order to equalize the time from application of a read command to actual arrival of read data for each sync link DRAM. The read latency is designated on the basis of a half cycle of control clock signal CCLK. With respect to the delay amount of read clock signal DCLK, the delay amount relative to control clock signal CCLK is determined by a command called a "read data vernier", and the offset between read clock signal DCLK and data is also given from a data offset vernier. By once setting read clock signal DCLK at the L level, a data sampling edge can be adjusted in its head cycle in controller 900.
By transferring data in synchronization with the rising and falling edges of clock signal DCLK as shown in FIG. 11, data can be transferred at high speed.
FIG. 12 schematically shows a structure of the data input portion of controller 900. In FIG. 12, the input portion of controller 900 includes a delay circuit 910 delaying read clock signal DCLK on clock signal line 906 by a prescribed time period, an input buffer 912 receiving data D supplied on data bus 908 at the rising and falling edges of a delayed clock signal DCLK.sub.-- D from delay circuit 910, and a data S/P (Serial/Parallel) converter 914 converting data on an internal high speed bus intData.sub.-- F from input buffer 912 to parallel data in accordance with control clock signal CCLK for transmission to low speed data buses intData&lt;0&gt; and intData&lt;1&gt;. When the frequency of an external interface is high, the internal portion of the controller usually operates in accordance with a frequency-divided clock signal of control clock signal CCLK. Especially, since data is transferred at the frequency twice as high as control clock signal CCLK, the data transfer frequency is halved by data S/P converter 914 to operate internal circuitry at the frequency of control clock signal CCLK.
FIG. 13 shows one example of the structure of the input buffer shown in FIG. 12. In FIG. 13, input buffer 912 includes an inverter 912a inverting delayed clock signal DCLK.sub.-- D, a transfer gate 912b formed of an n channel MOS transistor rendered conductive to allow data D to pass therethrough when the output signal of inverter 912a is at the H level, an inverter latch 912c latching the data received from transfer gate 912b, an inverter 912i inverting the latched data of inverter latch 912c, a transfer gate 912d formed of an n channel MOS transistor rendered conductive to allow the output signal of inverter 912i to pass therethrough when delayed clock signal DCLK.sub.-- D is at the H level, a transfer gate 912e formed of an n channel MOS transistor rendered conductive to allow data D to pass therethrough when delayed clock signal DCLK.sub.-- D is at the H level, an inverter latch 912f latching the data received from transfer gate 912e, an inverter 912g inverting the latched data of inverter latch 912f, and a transfer gate 912h formed of an n channel MOS transistor rendered conductive to transmit the output signal of inverter 912g to internal high speed data bus intData.sub.-- F when the output signal of inverter 912a is at the H level.
In the structure of input buffer 912 shown in FIG. 13, when one inverter latch latches external data, the other inverter latch transmits the latched data to internal high speed data bus intData.sub.-- F. Therefore, inverter latches 912c and 912f alternately perform the latching operation at each of H and L levels of delayed clock signal DCLK.sub.-- D. Thus, different data is transmitted to internal high speed data bus intData.sub.-- F each time delayed clock signal DCLK.sub.-- D changes.
FIG. 14 shows one example of the structure of data S/P converter 914 shown in FIG. 12. In FIG. 14, data S/P converter 914 includes an inverter 914a inverting control clock signal CCLK, a transfer gate 914b formed of an n channel MOS transistor rendered conductive to allow data on internal high speed data bus intData.sub.-- F to pass therethrough when the output signal of inverter 914a is at the H level, an inverter latch 914c latching the data received from transfer gate 914b, a transfer gate 914d formed of an n channel MOS transistor rendered conductive to allow the latched data of inverter latch 914c to pass therethrough when control clock signal CCLK is at the H level, an inverter latch 914e transmitting the data received through transfer gate 914d to a first internal low speed data bus intData&lt;0&gt;, a transfer gate 914f formed of an n channel MOS transistor rendered conductive to allow the data on internal high speed data bus intData.sub.-- F to pass therethrough when control clock signal CCLK is at the H level, an inverter latch 914g latching the data received through transfer gate 914f, a transfer gate 914h formed of an n channel MOS transistor rendered conductive to allow the latched data of inverter latch 914g to pass therethrough when the output signal of inverter 914a is at the H level, and an inverter latch 914i latching the data received from transfer gate 914h and transmitting it to a second internal low speed data bus intData&lt;1&gt;.
In data S/P converter 914 shown in FIG. 14, new data is transmitted in each clock cycle of control signal CCLK to internal low speed data buses intData&lt;0&gt; and intData&lt;1&gt;. In data S/P converter 914, the speed of transferring internal data is that of half the frequency of control signal CCLK. However, conversion into divided-by-three or more frequency of the control clock signal may be performed. Then, the operation of a control data input portion shown in FIGS. 12-14 will be described with reference to a timing chart shown in FIG. 15.
As shown in FIG. 15, the phases of control clock signal CCLK and read clock signal DCLK which is output from the sync link DRAM are shifted from each other. Such shifting is caused by the propagation delay of a signal on the read clock signal line because data is transferred through data bus 908 and read clock signal DCLK is also transmitted through clock signal line 906. Read clock signal DCLK and data D are transferred in synchronization, that is, in phase with each other (when the data offset vernier is set at 0).
Delay circuit 910 shown in FIG. 12 delays read clock signal DCLK by a prescribed time period to generate delayed clock signal DCLK.sub.-- D. In accordance with delayed clock signal DCLK.sub.-- D, data transmitted from a sync link DRAM is taken in, latched, and transferred to the internal data bus. When delayed clock signal DCLK.sub.-- D is at the H level, transfer gates 912d and 912e are conductive and transfer gates 912b and 912h are non-conductive in the input buffer shown in FIG. 13. Therefore, data D0 latched by inverter latch 912c is transmitted to internal high speed data bus intData.sub.-- F when delayed clock signal DCLK.sub.-- D is at the L level. At this time, inverter latch 912f takes in the next data. Therefore, data D0, D1, D2 and D3 are successively output to internal high speed data bus intData.sub.-- F each time delayed clock signal DCLK.sub.-- D changes.
Data S/P converter 914 operates in synchronization with control clock signal CCLK. In data S/P converter 914, data latched by inverter latch 914c is transmitted to internal low speed data bus intData&lt;0&gt; and data on internal low speed data bus intData&lt;1&gt; is latched when control clock signal CCLK is at the H level. When control clock signal CCLK attains the L level, the data on internal low speed data bus intData&lt;0&gt; is latched and new data is transmitted onto internal low speed data bus intData&lt;1&gt;. To internal low speed data buses intData&lt;0&gt; and intData&lt;1&gt;, data is alternately transmitted in each clock cycle of control clock signal CCLK. Thus, the data transmitted at the speed twice as high as control clock signal CCLK can be converted into those at the speed of control clock signal CCLK. Controller 900 operates in synchronization with control clock signal CCLK. Therefore, data transfer in accordance with the operation speed of a controller can be implemented.
FIG. 16 shows timing for reading data of each sync link DRAM in the sync link DRAM memory system shown in FIG. 10. As shown in FIG. 10, the distance from the controller is different for each sync link DRAM in the memory system. When the controller outputs a command, therefore, the time required for read clock signal DCLK and read data to arrive at the controller is different for a different addressed sync link DRAM. Read clock signal DCLK and data from sync link DRAM&lt;0&gt;(S#0) which is arranged closest to the controller arrives at the controller first. Read clock signal DCLK from a sync link DRAM&lt;1&gt;(S#1) which is adjacent to sync link DRAM&lt;0&gt; delays by time d1 from the read clock from sync link DRAM&lt;0&gt;. The read clock signal from a sync link DRAM&lt;7&gt;(S#7) which is arranged farthest from the controller arrives much later.
As shown in FIG. 16, read clock signal DCLK from sync link DRAM&lt;7&gt; arrives delayed by time d2 relative to read clock signal DCLK from sync link DRAM&lt;0&gt;. The read latency is defined on the basis of a half cycle of control clock signal CCLK. Even if the read latency is the same, therefore, the time from application of a command from the controller to actual arrival of the read clock signal and data is different. Accordingly, a data input error as described below is caused in the controller.
FIG. 17 shows operation timings where there is a data input error. In FIG. 17, an operation is represented where the propagation delay of the data bus and the read clock signal line is large and the phase difference between read clock signal DCLK and control clock signal CCLK is made small. In the controller, read clock signal DCLK is delayed to generate delayed clock signal DCLK.sub.-- D. When the delay by the delay circuit is larger than the delay time corresponding to the phase difference between read clock signal DCLK and control clock signal CCLK, the rising timing of delayed clock signal DCLK.sub.-- D is delayed from the rising timing of control clock signal CCLK.
Read clock signal DCLK and data are output at the same timing. To internal high speed data bus intData.sub.-- F, valid data D0 is initially output from input buffer 912 when control clock signal CCLK is raised. Therefore, data S/P converter 914 performs a latching operation in synchronization with a rising of control clock signal CCLK and transmits invalid data to internal low speed data bus intData&lt;0&gt;. The first valid data D0 is transmitted to another internal low speed data bus intData&lt;1&gt;. Thus, data D1 and D3 are transmitted to internal low speed data bus intData&lt;0&gt;, and data D0 and D2 are transmitted to internal low speed data bus intData&lt;1&gt;. In the controller, therefore, even numbered data and odd numbered data are reversely processed, resulting in an incorrect processing.
In order to prevent an error in transferring data which is caused by the influence of data propagation delay due to the distance from the controller to a sync link DRAM so that data can arrive at the controller at the same timing whichever sync link DRAM is accessed, it has been proposed to perform adjustment of the output delay called "vernier control" at the time of initialization.
The "vernier control" is adjustment of the output timing of each sync link DRAM by sending a vernier control command to the sync link DRAM at the time of initialization so as to achieve the timing at which the controller can input data correctly. After the controller sets the slave ID of each sync link DRAM, and then sets the H and L voltage levels of each output signal as well as an operating frequency, a read timing synchronization sequence for the vernier control is performed. In the read timing synchronization sequence, when the controller provides a read synchronization request command to a sync link DRAM, each sync link DRAM sends a data pattern having a known-pattern back to the controller. When the controller sends out the synchronization request command, it repeatedly sends out the synchronization request commands until a known data pattern is sent back and received at optimum timing. In the sync link DRAM, in this sequence, by using the count value of a built-in counter the delay of data outputting with respect to the control clock signal is increased or reduced on the basis of a unit amount in accordance with a command applied from the controller. Thus, the timing for outputting data is finely adjusted.
FIG. 18 schematically shows a structure of the data output portion of the sync link DRAM. In FIG. 18, the output portion of the sync link DRAM includes a vernier 950 changing the delay amount of an internal clock signal CLK.sub.-- O generated at the time of data reading and generating a vernier clock signal VCLK.sub.-- O in accordance with an externally applied increment/decrement command UP/DOWN, output buffers OB0-OB7 receiving internal read data intD&lt;0&gt;-intD&lt;7&gt; and outputting them in parallel to data buses &lt;0&gt;-&lt;7&gt; in synchronization with vernier clock signal VCL.sub.-- O, and a DCLK output buffer COB buffering vernier clock signal VCLK.sub.-- O and outputting read clock signal DCLK. Here, the structure in which the data bus has a width of 8 bits, and eight output buffers are provided in parallel is shown as one example.
Vernier 950 changes the delay amount with respect to clock signal CLK.sub.-- O in accordance with externally applied increment/decrement command UP/DOWN. Now, the operation of the output portion shown in FIG. 18 will be described with reference to a flow chart shown in FIG. 19A and a timing chart shown in FIG. 19B.
First, as shown in FIG. 19A, a read sync request command is sent out from the controller to a corresponding sync link DRAM in order to set read timing (step S1). The read sync request command instructs the sync link DRAM of interest to output data having a prescribed pattern. The sync link DRAM sends the prescribed synchronization pattern to the controller in accordance with the read sync request command. The controller activates the internal synchronization circuit when it sends the read sync request command, and determines whether the synchronization pattern is received or not based on reception of the prescribed data pattern (step S2). When the synchronization pattern is received, the controller then determines whether the timing for reception is optimum (step S3). The determination is made based, for example, on whether control clock signal CCLK changes at the center of a bit. When the controller determines that the timing for reception is not optimum, it determines whether the timing is advanced or lagged (step S4) and, based on the result of the determination, sends a command instructing the increment or decrement of the vernier (count value) to the corresponding sync link DRAM (step S5).
As shown in FIG. 19B, in the sync link DRAM, the delay amount of vernier 950 is updated in accordance with the increment/decrement command to adjust the phase difference between clock signal CLK.sub.-- O and vernier clock signal VCLK.sub.-- O. Then, the operation from step 1 is repeated. When the timing for reception is determined to be optimum at step S3, the operation for adjusting the read timing is completed.
As a result of vernier adjustment, as shown in FIG. 19B, control clock signal CCLK changes almost at the center of delayed clock signal DCLK.sub.-- D, and data D0, D1, D3 . . . on internal high speed data bus intData.sub.-- F are received and successively transferred to internal low speed data buses intData&lt;O&gt; and intData&lt;1&gt; in the controller. Therefore, even when the distance from the controller is different for each sync link DRAM, an optimum delay amount (fine read vernier) is set for each sync link DRAM and correct data reception is achieved in the controller.
Various specifications have been made for the sync link DRAM. With respect to adjustment of a data read vernier, however, adjustment of the timing for clock generation by increasing and decreasing the count value of a built-in counter of the sync link DRAM has only been described. A specific circuit example has not been described.
FIG. 20A shows one possible example of a circuit for adjusting the phase of a clock signal by using such a counter. In FIG. 20A, vernier circuit 950 includes a delay circuit DLC formed of cascaded inverters of 2 m stages for delaying clock signal CLK.sub.-- O, a counter 955 having its count value increased and decreased in accordance with an increment command UP and a decrement command DOWN, and a selection circuit ST selecting the output of delay circuit DLC in accordance with the output count value of counter 955.
Delay circuit DLC includes delay stages DL1-DLm each having cascaded inverters of two stages. Counter 955 has output count bits C0!-Cm! corresponding to the inputs and the outputs of delay stages DL1-DLm. In counter 955, the count value is initialized in accordance with reset signal ZRST.
Selection circuit ST includes transfer gates T&lt;0&gt;-T&lt;m&gt; provided corresponding to delay stages DL1-DLm of delay circuit DLC and each formed, for example, of an n channel MOS transistor for selecting the output of a corresponding delay stage or input clock signal CLK.sub.-- O in response to a corresponding one of output count bits C0!-Cm! of counter 955. Only one of output count bits C0!-Cm! is activated in counter 955 and only one corresponding transfer gate is rendered conductive in selection circuit ST, so that a corresponding delayed clock signal or input clock signal CLK.sub.-- O is selected from delay circuit DLC to output vernier clock signal VCLK.sub.-- O. In the structure shown in FIG. 20A, the phase of clock signal CLK.sub.-- O can be adjusted by the step of the delay time of delay stages DL1-DLm.
FIG. 20B shows a structure of counter 955 shown in FIG. 20A. In FIG. 20B, counter 955 has count circuits CTR0-CTRm provided corresponding to count bits C0!-Cm!. Count circuit CRT0 includes an inverter 956, an NAND circuit 957 receiving the output signal of inverter 956 and a reset instruction ZRST and supplying the output to inverter 956, a transfer gate 958 formed of an n channel MOS transistor rendered conductive to transfer the output signal S0! of inverter 956 in response to a transfer instruction signal T0, an inverter latch 959 latching a signal transmitted by transfer gate 958, and a transfer gate 960 formed of an n channel MOS transistor transmitting count bit C0! latched by inverter latch 959 to a count circuit CTR1 at the next stage in accordance with decrement command DOWN. The input of inverter 956 is reset at a ground voltage GND (logic 0) by an n channel MOS transistor 961 which is rendered conductive in response to decrement command DOWN.
Since count circuits CTR1-CTRm-1 have the same structure, count circuit CTR1 is representatively shown in FIG. 20B. Count circuit CTR1 includes an inverter 963, an NAND circuit 962 receiving reset instruction signal ZRST and the output signal of inverter 963 and supplying the output to inverter 963, a transfer gate 964 rendered conductive to transmit the output signal of NAND circuit 962 in response to transfer instruction signal T0, an inverter latch 965 latching data transferred by transfer gate 964, a transfer gate 966 transmitting data C1! latched by inverter latch 965 to a count circuit CTR2 at the next stage in response to activation of decrement command DOWN, and a transfer gate 967 rendered conductive to send count bit C1! latched by inverter latch 965 back to the input portion of count circuit CTR0 at a previous stage in response to activation of increment command UP.
Count circuit CTRm at the last stage includes an NAND circuit 971 receiving data transferred by count circuit CTRm-1 (not shown) at the previous stage and reset instruction signal ZRST, an inverter 972 receiving the output signal Sm! of NAND circuit 971 for transference to the input of NAND circuit 971, a transfer gate 973 rendered conductive to transfer the output signal of NAND circuit 971 in response to activation of transfer instruction signal T0, an inverter latch 974 latching data transferred by transfer gate 973 and outputting count bit Cm!, and a transfer gate 975 rendered conductive to send count bit Cm! latched by inverter latch 974 back to the input portion of count circuit CTRm-1 at the previous stage in response to activation of increment command UP. Since a count circuit does not exist at the next stage, count circuit CTRm at the last stage is not provided with a transfer gate responsive to decrement command DOWN.
FIG. 20C shows a structure of a circuit for generating transfer instruction signal T0. The transfer instruction signal generation portion includes an NOR circuit 980 receiving decrement command DOWN and increment command UP. When the increment or decrement operation is performed, transfer instruction signal T0 attains the L level inactive state and a count bit supplied from the count circuit at the previous stage is taken in and latched. Now, the operation of vernier circuit 950 shown in FIGS. 20A-20C will be described with reference to a timing chart shown in FIG. 21.
At time t0, a vernier setting operation is designated and reset signal ZRST is set at the L level for a prescribed time period. In response to a fall of reset signal ZRST, the output signal of NAND circuit 957 attains the H level and accordingly the output signal of inverter 956 attains the L level in count circuit CTR0. Therefore, an internal signal S0! is initialized to the L level. Since increment command UP and decrement command DOWN are both at the L level, transfer instruction signal T0 is at the H level, transfer gate 958 is rendered conductive, and count bit C0! latched by inverter latch 959 is set at the H level (logic "1"). In the remaining count circuits CTR1-CTRm, output signals S1!-Sm! of NAND circuits 962 and 971 attain the H level in response to a fall of reset instruction signal ZRST to the L level, and count bits Cl!-Cm! latched by inverter latches 965 and 974 are set at the L level (logic "0").
By the operation above, initialization is performed and only count bit C0! keeps its active state. In this state, only transfer gate T&lt;0&gt; shown in FIG. 20A is rendered conductive and read clock signal CLK.sub.-- O is selected as vernier clock signal VCLK.sub.-- O.
At time t1, decrement command DOWN is activated, transfer gates 961, 960, 966 are rendered conductive, and the shift operation of the count bits corresponding to count circuits CTR0-CTRm is performed. While decrement command DOWN is at the H level, transfer instruction signal T0 is at the L level. Thus, transfer gates 958, 964 and 973 are all non-conductive and count bits C0!-Cm! do not change. By this transfer operation, output signal S1! of NAND circuit 962 is lowered from the H level to the L level in count circuit CTR1 (reset signal ZRST is at the H level non-active state), and internal signals Si! of remaining count circuits CTR2-CTRm all keep the H level. In count circuit CTR0 at the first stage transistor 961 is rendered conductive and ground voltage GND is transmitted, and internal signal S0! is lowered to the H level.
When decrement command DOWN is lowered to the L level at time t2, transfer gates 958, 964 and 973 are rendered conductive in count circuits CTR0-CTRm, so that internal signals are transferred and the count bits are updated. In this case, count bit C0! is lowered from logic 1 to logic 0. On the other hand, in count circuit CTR1, L level signal Sl! is latched by inverter latch 965 and count bit C1! is raised to logic 1. The count bits are not changed in remaining count circuits CTR2-CTRm. In this state, only transfer gate T&lt;1&gt; shown in FIG. 20A is rendered conductive and the output signal of delay stage DL1 is selected as vernier clock signal VCLK.sub.-- O.
At time t3, decrement command DOWN attains the H level active state again, and the internal transfer operation of the count bit is performed. In this case, the internal signal of count circuit CTR2 is at the L level while internal signals Si! of remaining count circuits are at the H level.
When decrement command DOWN is lowered to the L level at time t4, transfer instruction signal T0 attains the H level and transfer gates 958, 964 and 973 are rendered conductive to transfer the internal signals to corresponding inverter latches. In this case, count bit C2! changes to the H level (logic 1) while remaining count bits C0! and C2!-Cm! keep the L level (logic 0). In this case, transfer gate T&lt;2&gt; shown in FIG. 20A is rendered conductive and the output signal of delay stage DL2 is selected as vernier clock signal VCLK.sub.-- O.
At time t5, increment command UP rises to the H level and accordingly transfer instruction signal T0 attains the L level. In this case, the data latched by the inverter latch of each count circuit is transferred to the input portion of the count circuit at the previous stage. Therefore, count bit C2! of count circuit CTR2 is transferred to the input portion of count circuit CTR1, and internal signal S1! is lowered to the L level. Meanwhile, in count circuit CTR2, internal signal S2! is raised to the H level by a feedback signal from count circuit CTR3 (not shown).
When increment command UP attains the L level at time t6, transfer instruction signal T0 attains the H level and the signal taken in inside is transferred to the inverter latch. In this case, only internal signal S1! of count circuit CTR1 is at the L level and the internal signals of remaining count circuits CTR0 and CTR2-CTRm are at the H level. Therefore, in response to the fall of increment command UP at time t6, count bit C1! is raised to the H level (logic 1) and count bit C2! changes to the L level (logic 0). In this case, transfer gate T&lt;1&gt; shown in FIG. 20A is rendered conductive again and the output signal of delay stage DL1 is selected as vernier clock signal VCLK.sub.-- O.
In the case of the vernier circuit shown in FIGS. 20A-20C, the delay time of a clock signal can be adjusted with the delay time caused by inverters of two stages used as a minimum unit.
In other words, in the vernier circuit shown in FIGS. 20A-20C, application of command UP shortens the delay time of vernier clock signal VCLK.sub.-- O while application of command DOWN lengthens the delay time of vernier clock signal VCLK.sub.-- O. In the controller, applied data can correctly and selectively be transferred to internal data buses intData&lt;0&gt; and intData&lt;1&gt; by timing adjustment.
FIG. 22 shows a structure of an inverter included in delay circuit DLC. In FIG. 22, the inverter includes a p channel MOS transistor PQ rendered conductive to drive an output signal OUT to a power supply voltage VDD level when an input signal IN is at the L level, and an n channel MOS transistor NQ rendered conductive to discharge output signal OUT to the ground voltage GND level when input signal IN is at the H level. With such MOS transistors, when power supply voltage VDD becomes higher, the source voltage of MOS transistor PQ is accordingly raised, increasing the amount of driving current of MOS transistor PQ and allowing the rise of output signal OUT at high speed. When the internal power supply voltage becomes higher, the H level of input signal IN is raised. Therefore, the gate voltage of MOS transistor NQ is raised and accordingly the amount of driving current of MOS transistor NQ is increased. On the contrary, when the internal power supply voltage is lowered, the current drivability of MOS transistors PQ and NQ is reduced, lowering the transition speed of output signal OUT.
Further, when operating temperature is raised, hot electrons are generated in an MOS transistor and collision of electric charges is caused in the channel region, so that the channel resistance is increased equivalently. Therefore, higher operating temperature lowers the transition speed of output signal OUT.
Therefore, in the case of a structure in which a delay circuit is formed of an inverter and the output of the delay circuit is selected, the delay time of each output stage changes in accordance with changes in an operating power supply voltage and operating temperature. Vernier setting is performed at the time of initialization but will not be performed during the operation thereafter. Therefore, it is necessary to power up the system again by resetting the system in order to carry out a resetting. Thus, when the operating power supply voltage and operating temperature of each sync link DRAM change during the operation, the value of the read vernier which is initially set changes and the controller cannot input data at correct timing. Accordingly, internal data transfer cannot be performed correctly.